The present invention relates to a read only memory, and especially to flat memory cell read only memory for reading data quickly.
Currently, in designing integrated circuit (IC), speed, size, power, cost and manufacturing process are main considerations. Most of IC designs require to reduce power supply and size, and have a preferred speed. In prior art, there are several read only memories for reading memory cell data are developed. One is a flat memory cell read only memory.
In a flat memory cell field effect transistor, at first, since the width of the polysilicon wordline determines the channel width of the field effect transistor instead of the length of the channel so that a polysilicon wordline is formed by the concept of the extremity of the manufacturing process. Furthermore, since the central section of the ROM has no field oxide layer formed by heating growth, and thus there is no defect of the channel reduction due to bird""s beak effect. Therefore, flat memory cell read only memory has a dense memory cell array. Other than the size of the memory cells, the size of the ROM array is affected by the circuit of the ROM memory cells and the peripheral circuits.
Therefore, for ROM, an optimum method is to confine the number of transistors for reading the ROM and properly using the surface area of a semiconductor, thereby providing small size and easy manufacturing semiconductor elements. Comparing with other designing ways, the use of flat memory cause that each ROM has a very small area.
The prior art flat memory cell read only memory, such as U. S. Pat. No. 5, 117,389, xe2x80x9cFlat Memory Cell Read Only Memory Integrated Circuitxe2x80x9d, in that selecting transistors of block selecting word lines BWLN, selecting transistors of polysilicon wordlins SWLN, selecting transistors of left side selecting lines SBLN, and selecting transistors of right side selecting lines SBRN are required to read data of ROM memory cells. In the design, at least four transistors are required to read data of the ROM memory cells. Therefore, the operation time is long and speed is low. There are many transistors required for reading data of the memory cells. This will affect the size of the memory array, while other generated peripheral circuits will also affect the size of the whole array. These are defects of the U. S. patent.
Accordingly, the primary object of the present invention is to provide a flat memory cell read only memory, wherein commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.
Another object of the present invention is to provide a flat memory cell read only memory, wherein straight metal lines are used to read data of metal bitlines so as to have a high density layout and has a dense memory cell array.
To achieve the object, the flat memory cell read only memory of the present invention includes a plurality of sub-arrays. Each sub-array utilizes a plurality of diffusion area, insulating layers, memory cell selecting transistors, for a plurality of metal bitlines, polysilicon word lines, memory cells, and four block selecting lines for reading data on the memory cell.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.